tdc_ms1030.c 15 KB

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  1. #include "board.h"
  2. #include "tdc_tof.h"
  3. #define ANZ_FIRE 12u //fire发送脉冲数
  4. #define DIV_FIRE 3u //内部时钟产生脉冲的分频
  5. #define DIV_CLKHS 0u //高速时钟分频
  6. #define START_CLKHS 2u //高速启动后测量前晶振启动间隔时间,120us
  7. #define NEG_START 0u //start通道边缘
  8. #define NEG_STOP 0u //stop通道边缘
  9. #define HITIN 9u //stop预期脉冲数
  10. #define SEL_TIMO_MB 0u //暂未确定数值
  11. #define SEL_TSTO2 3u //32khz //和MS1030不同
  12. #define SEL_TSTO1 0u //暂时不用这个引脚,配置为高速时钟输入模式
  13. #define DFLT_WREG0 ((ANZ_FIRE<<25) | \
  14. ( DIV_FIRE<<19) | \
  15. ( DIV_CLKHS<<17) | \
  16. ( START_CLKHS<<14) | \
  17. ( NEG_START<<13) | \
  18. ( NEG_STOP<<12) | \
  19. ( HITIN<< 8) | \
  20. ( SEL_TSTO2<< 2) | \
  21. ( SEL_TSTO1<< 0))
  22. #define EN_INT_TO 1 //TIMOUT中断触发位
  23. #define EN_INT_HIT 0 //END HITS中断触发位
  24. #define EN_INT_ALU 1 //alu中断触发位
  25. #define RFEDGE 0 //stop通道边沿敏感性
  26. #define UP_DELVAL1 0 //当EN_FIST_WAVE=1时,为第一波屏蔽窗口 BIT12~27 暂未设置
  27. #define OFFSET 0 //当en_hc=1时, 62~-64mV 暂未设置
  28. #define DFLT_WREG1 (( EN_INT_TO<<31) | \
  29. ( EN_INT_HIT<<30) | \
  30. ( EN_INT_ALU<<29) | \
  31. ( RFEDGE<<28) | \
  32. ( UP_DELVAL1<<12) | \
  33. ( OFFSET<< 0))
  34. #define EN_FIRST_WAVE 0u //BIT31, 为1时后面的定义有效
  35. #define EDGE_FW 0u //第一波边缘敏感性
  36. #define DELREL1 6u //第1个stop接收第几个回波周期
  37. #define DELREL2 8u //第2个stop接收第几个回波周期
  38. #define DELREL3 10u //第3个stop接收第几个回波周期
  39. #define DELREL4 12u //第4个stop接收第几个回波周期
  40. #define DELREL5 14u //第5个stop接收第几个回波周期
  41. #define DFLT_WREG2 ((EDGE_FW<<30) | \
  42. (DELREL1<<24) | \
  43. (DELREL2<<18) | \
  44. (DELREL3<<12) | \
  45. (DELREL4<< 6) | \
  46. (DELREL5<< 0))
  47. #define DELREL6 16u //第3个stop接收第几个回波周期
  48. #define DELREL7 18u //第4个stop接收第几个回波周期
  49. #define DELREL8 20u //第5个stop接收第几个回波周期
  50. #define DFLT_WREG3 ((DELREL6<<26) | \
  51. (DELREL7<<20) | \
  52. (DELREL8<<14))
  53. #define CONF_FIRE 0 //暂时设置为0 bit29~31
  54. #define PHASE_FIREUP 0
  55. #define PHASE_FIREDOWN 0
  56. #define SEL_START_FIRE 1
  57. #define EN_ANALOG 1
  58. #define HZ60 0
  59. #define TCYCLE 1
  60. #define ANZ_FAKE 0
  61. #define SEL_ECLK_TMP 1
  62. #define TW2 1 //120us充电时间,与1030不同
  63. #define EN_PEAK 0 //峰值检波使能关闭,1030不同
  64. #define EN_DISCHARGE 0 //检波放电使能关闭,1030不同
  65. #define CYCLE_TOF 3 //顺流逆流自动检测模式下,顺流逆流测量间隔时间,初步确定为3=20ms 1030不同
  66. #define EN_ERR_VAL 1
  67. #define EN_DC 1 //stop端口充电模式 这里设置为直流 1030不同
  68. #define FIRE0_DEF 1 //fire通道默认电平
  69. #define DOUBLE_RES 0
  70. #define QUAD_RES 1
  71. #define DFLT_WREG4 (( PHASE_FIREUP<<28) | \
  72. ( PHASE_FIREDOWN<<27) | \
  73. ( SEL_START_FIRE<<26) | \
  74. ( EN_ANALOG<<25) | \
  75. ( HZ60<<24) | \
  76. ( TCYCLE<<23) | \
  77. ( ANZ_FAKE<<22) | \
  78. ( SEL_ECLK_TMP<<21) | \
  79. ( TW2<<17) | \
  80. ( EN_PEAK<<16) | \
  81. ( EN_DISCHARGE<<15) | \
  82. ( CYCLE_TOF<<11) | \
  83. ( EN_ERR_VAL<<10) | \
  84. ( EN_DC<<9) | \
  85. ( FIRE0_DEF<<8) | \
  86. ( DOUBLE_RES<<7) | \
  87. ( QUAD_RES<<6))
  88. #define CYCLE_AUTOTOF (250<<20) //自动测量循环时间 500ms
  89. #define ANZ_AUTOTOF (1<<16) //循环次数 一直开启
  90. #define AUTOTOF_MODE (0<<15) //顺逆顺逆
  91. #define PHASE_FIRENUM (3<<6) //插入相位位置
  92. #define ANZ_PHASE (8) //插入周期数
  93. #define DFLT_WREG5 0
  94. #define DOWN_DELVAL1 (0<<12)//第一波屏蔽窗口
  95. #define SEL_SRC_CLK (0<<7)//使用晶振产生时钟
  96. #define EN_HC (1<<6)
  97. #define CURR32K (0<<5)
  98. #define DIS_Vref (1<<4)
  99. #define ADJ_LDO_ROUGH (0<<3)
  100. #define ADJ_LDO_FINE (4<<0)
  101. #define DFLT_WREG6 (DOWN_DELVAL1|SEL_SRC_CLK|EN_HC|CURR32K|DIS_Vref|ADJ_LDO_ROUGH|ADJ_LDO_FINE)
  102. uint16_t tof_state = TOF_ST_INIT;
  103. uint32_t tof_flag;
  104. //uint16_t CntSync = 0;
  105. void tdc_tof_init(void)
  106. {
  107. //MUX ADDA : PA08; ADDB : PC09
  108. mux_init();
  109. // MS1030 RSTN : PD02
  110. GpioInit(PD02_AF0, GPIO_DIG_OUT_WEAK_PUSH_NONEUP_NONEDOWN);
  111. GpioClrPins(GpioPortD, GpioBitMsk2); // reset active low
  112. us_delay(10); // 10us > tPH(30ns)
  113. GpioSetPins(GpioPortD, GpioBitMsk2); // reset release
  114. us_delay(10); // 10us > tRFS(30ns)
  115. tdc_spi_init(); // peripheral init
  116. PeriClk_MutEnable(PeriClk_Spi1);
  117. DMA_ReqClkOn();
  118. // TDC POR
  119. tdc_spi_wr_code(0x50);
  120. us_delay(1000); // 1000us > specification(500us)
  121. // tdc_spi_wr_d32(0x80, 0x1E18884E); // 修正:SEL_TIMO_MB = 8(合法)
  122. // tdc_spi_wr_d32(0x81, 0xA00C8005);
  123. // tdc_spi_wr_d32(0x82, 0x83105187);
  124. // tdc_spi_wr_d32(0x83, 0x20928400);
  125. // tdc_spi_wr_d32(0x84, 0x66E00540);
  126. // tdc_spi_wr_d32(0x85, 0x07D10000);
  127. // tdc_spi_wr_d32(0x86, 0x000C8004);
  128. tdc_spi_wr_d32(0x80, DFLT_WREG0);
  129. uint32_t read_a0=tdc_spi_rd_d32(0xA0);
  130. read_a0=read_a0&0xFFu;
  131. #if 1
  132. tof_flag = TOF_FLAG_UNALGND_CHOP;
  133. if (read_a0!=(DFLT_WREG0&0xFFu)){
  134. tof_flag |= TOF_FLAG_TDC_FAULT;
  135. } else {
  136. // write_reg0
  137. tdc_spi_wr_d32(0x80, DFLT_WREG0 |
  138. ( 2u<< 4) // SEL_TIMO_MB, 0:64us; 1:128us; 2:256us; ~ 6:4096us;
  139. );
  140. // write_reg1
  141. tdc_spi_wr_d32(0x81, DFLT_WREG1 |
  142. (5760u<< 12) // DELVAL1=45us, format:16.5, time unit:Tref;
  143. );
  144. // write_reg2
  145. tdc_spi_wr_d32(0x82, DFLT_WREG2 |
  146. ( 0u<<31) // EN_FIRST_WAVE, 0:disable; 1:enable;
  147. );
  148. // write_reg3
  149. tdc_spi_wr_d32(0x83, DFLT_WREG3 |
  150. ( 1u<<13) // measure FW pulse width, 0:on; 1:off
  151. );
  152. // write_reg4
  153. tdc_spi_wr_d32(0x84, DFLT_WREG4);
  154. // write_reg5
  155. tdc_spi_wr_d32(0x85, DFLT_WREG5);
  156. // write_reg6
  157. tdc_spi_wr_d32(0x86, DFLT_WREG6);
  158. tdc_spi_wr_code(0x70);
  159. tdc_spi_wr_code(0x06);
  160. // not 'INTN' but 'us_delay' to avoid dead loop when INTN fault
  161. us_delay(2000); // > 480 + 600 + 16 + 70
  162. tdc_read_cal(0x0u);
  163. // tof_flag ^= TOF_FLAG_UNALGND_CHOP;
  164. // // start a single ToF to align MS1030 internal calibration order(1 CAL every 24 ToF)
  165. // // must be sure that CAL not in the middle of UP Tof and DOWN Tof
  166. // tdc_start_tof(TDC_CFG_DO_WREG | TDC_CFG_FIRE_UP);
  167. //
  168. // // not 'INTN' but 'us_delay' to avoid dead loop when INTN fault
  169. // us_delay(2000); // > 480 + 600 + 16 + 70
  170. //
  171. // tdc_read_tof(TDC_CFG_FIRE_UP); // read data and clear interrupt
  172. }
  173. #endif
  174. DMA_ReqClkOff();
  175. PeriClk_MutDisable(PeriClk_Spi1);
  176. // MS1030 INTN : PD03 falling edge trigger
  177. GpioInit(PD03_AF0, GPIO_DIG_IN_PULLUP_NONEDOWN);
  178. GpioEventInit(PD03_AF0, GPIO_EVENT_FALL);
  179. // enable interrupt at NVIC side
  180. IRQMutEnable(PORTD_F_IRQn, NVIC_PRIO_1);
  181. }
  182. void tdc_start_tof(uint32_t cfg)
  183. {
  184. //rt_enter_critical();
  185. uint32_t u32tmp;
  186. if (cfg & TDC_CFG_DO_CKENA){
  187. PeriClk_MutEnable(PeriClk_Spi1);
  188. DMA_ReqClkOn();
  189. }
  190. if (cfg & TDC_CFG_DO_WREG){
  191. // write_reg0
  192. tdc_spi_wr_d32(0x80, DFLT_WREG0 |
  193. ( 3u<< 4) // SEL_TIMO_MB, 0:64us; 1:128us; 2:256us; ~ 6:4096us;
  194. //modified by yuewei 20260526 1->3, 128us -> 512us, for DN300 almost 240us
  195. );
  196. // write_reg1
  197. // DN15: L/C > (42+21+10*2)*1000/1555=53us
  198. tdc_spi_wr_d32(0x81, DFLT_WREG1 |
  199. (5760u<< 12) // DELVAL1=45us, format:16.5, time unit:Tref;//1031 从BIT12开始
  200. // (6400u<< 7) // DELVAL1=50us, format:16.5, time unit:Tref;
  201. // (7040u<< 7) // DELVAL1=55us, format:16.5, time unit:Tref;
  202. // (7680u<< 7) // DELVAL1=60us, format:16.5, time unit:Tref;
  203. // (8230u<< 7) // DELVAL1=65us, format:16.5, time unit:Tref;
  204. // (8960u<< 7) // DELVAL1=70us, format:16.5, time unit:Tref;
  205. );
  206. // write_reg2
  207. tdc_spi_wr_d32(0x82, DFLT_WREG2 |
  208. ( 1u<<31) // EN_FIRST_WAVE, 0:disable; 1:enable;
  209. );
  210. // write_reg3
  211. u32tmp = DFLT_WREG3 |
  212. ( 0u<<13) | // measure FW pulse width, 0:on; 1:off
  213. (TdcFwOfst<<6); // FW wave_offs, 0:0mv; 1~63:2~126mV; 64~127:-128~-2mV;
  214. if (tof_state&TOF_ST_VOID){
  215. u32tmp |= (1u<<13); // disable FW pulse width to save power
  216. }
  217. tdc_spi_wr_d32(0x83, u32tmp);
  218. }
  219. // write_reg4
  220. u32tmp = DFLT_WREG4;
  221. u32tmp |= (1u<<30); // FIRE_UP, 0:off; 1:on;
  222. tdc_spi_wr_d32(0x84, u32tmp);
  223. // Initial TDC status regs
  224. tdc_spi_wr_code(0x70);
  225. // start single-direction measure
  226. tdc_spi_wr_code(0x03);
  227. if (cfg & TDC_CFG_DO_CKDIS){
  228. DMA_ReqClkOff();
  229. PeriClk_MutDisable(PeriClk_Spi1);
  230. }
  231. //rt_exit_critical();
  232. }
  233. uint16_t TdcStatus;
  234. uint16_t TdcUPwFw;
  235. uint16_t TdcUPwHw;
  236. uint32_t TdcUToF[9];
  237. uint16_t TdcDPwFw;
  238. uint16_t TdcDPwHw;
  239. uint32_t TdcDToF[9];
  240. uint32_t TdcCal;
  241. //float TdcScale = 250.0f/65536;
  242. float TdcScale = 0.00381147861f;
  243. uint32_t TdcPT[4];
  244. float TdcResist = 5000; // OhmX10
  245. //modified by yuewei 20260520
  246. //float WaterPrmt[2] = {25.0f, 1496.6f};
  247. float WaterPrmt[2] = {25.0f, 1497.1484f};
  248. void tdc_read_tof(uint32_t cfg)
  249. {
  250. // uint16_t i;
  251. if (cfg & TDC_CFG_DO_CKENA){
  252. PeriClk_MutEnable(PeriClk_Spi1);
  253. DMA_ReqClkOn();
  254. }
  255. TdcStatus = tdc_spi_rd_d16(0xd0); // 读取状态寄存器
  256. if ((TdcStatus&0x0300)==0x0000u){
  257. tof_flag ^= TOF_FLAG_UNALGND_CHOP;
  258. // if (CntSync>=240){
  259. // CntSync = 10;
  260. // } else {
  261. // CntSync += 10;
  262. // }
  263. }
  264. if ((TdcStatus&0x03F0)!=0x0090u){
  265. tof_flag |= TOF_FLAG_BLANK_PIPE;
  266. tdc_spi_wr_code(0x70);
  267. }
  268. else
  269. {
  270. TdcUPwFw = tdc_spi_rd_d16(0xd3); // First wave pulse width
  271. TdcUPwHw = tdc_spi_rd_d16(0xd4); // 1st Hit wave pulse width
  272. tdc_spi_wr_code(0x70);
  273. // TOF_UP_HITs
  274. TdcUToF[0] = tdc_spi_rd_d32(0xb8)*(1.0f/8); // average of all
  275. // TOF_DOWN_HITs
  276. TdcDToF[0] = tdc_spi_rd_d32(0xc8)*(1.0f/8); // average of all
  277. // for(i=0; i<8; i++){
  278. // TdcDToF[i+1] = tdc_spi_rd_d32(0xb0 + i);
  279. // };
  280. }
  281. if (cfg & TDC_CFG_DO_CKDIS){
  282. DMA_ReqClkOff();
  283. PeriClk_MutDisable(PeriClk_Spi1);
  284. }
  285. }
  286. void tdc_start_cal(uint32_t cfg)
  287. {
  288. //rt_enter_critical();
  289. if (cfg & TDC_CFG_DO_CKENA){
  290. PeriClk_MutEnable(PeriClk_Spi1);
  291. DMA_ReqClkOn();
  292. }
  293. // 8*T_32k = 244.140625us
  294. if (cfg & TDC_CFG_DO_WREG){
  295. // write_reg0
  296. tdc_spi_wr_d32(0x80, DFLT_WREG0 |
  297. ( 2u<< 4) // SEL_TIMO_MB, 0:64us; 1:128us; 2:256us; ~ 6:4096us;
  298. );
  299. // write_reg3
  300. tdc_spi_wr_d32(0x83, DFLT_WREG3 |
  301. ( 1u<<13) // measure FW pulse width, 0:on; 1:off
  302. );
  303. }
  304. tdc_spi_wr_code(0x70);
  305. tdc_spi_wr_code(0x06);
  306. if (cfg & TDC_CFG_DO_CKDIS){
  307. DMA_ReqClkOff();
  308. PeriClk_MutDisable(PeriClk_Spi1);
  309. }
  310. //rt_exit_critical();
  311. }
  312. void tdc_read_cal(uint32_t cfg)
  313. {
  314. //rt_enter_critical();
  315. if (cfg & TDC_CFG_DO_CKENA){
  316. PeriClk_MutEnable(PeriClk_Spi1);
  317. DMA_ReqClkOn();
  318. }
  319. TdcStatus = tdc_spi_rd_d16(0xd0); // status
  320. if ((TdcStatus&0x0300)==0x0000u){
  321. tof_flag ^= TOF_FLAG_UNALGND_CHOP;
  322. // if (CntSync>=240){
  323. // CntSync = 10;
  324. // } else {
  325. // CntSync += 10;
  326. // }
  327. tdc_spi_wr_code(0x70);
  328. TdcCal = tdc_spi_rd_d32(0xd5);
  329. // TdcScale = 244140.625f/TdcCal;
  330. TdcScale += (244140.625f/TdcCal - TdcScale)*(1.0f/2);
  331. //LOG("----------TdcScale=%.6f\n",TdcScale);
  332. } else {
  333. tdc_spi_wr_code(0x70);
  334. }
  335. if (cfg & TDC_CFG_DO_CKDIS){
  336. DMA_ReqClkOff();
  337. PeriClk_MutDisable(PeriClk_Spi1);
  338. }
  339. //rt_exit_critical();
  340. }
  341. void tdc_start_temp(uint32_t cfg)
  342. {
  343. //rt_enter_critical();
  344. if (cfg & TDC_CFG_DO_CKENA){
  345. PeriClk_MutEnable(PeriClk_Spi1);
  346. DMA_ReqClkOn();
  347. }
  348. if (cfg & TDC_CFG_DO_WREG){
  349. // write_reg0
  350. tdc_spi_wr_d32(0x80, DFLT_WREG0 |
  351. ( 3u<< 6) // SEL_TIMO_MB, 0:64us; 1:128us; 2:256us; 3:512us; ~ 6:4096us;
  352. );
  353. // write_reg1
  354. tdc_spi_wr_d32(0x81, DFLT_WREG1 |
  355. ( 0u<< 12) // DELVAL1=0us, format:16.5, time unit:Tref;
  356. );
  357. // write_reg3
  358. tdc_spi_wr_d32(0x83, DFLT_WREG3 |
  359. ( 1u<<13) // measure FW pulse width, 0:on; 1:off
  360. );
  361. }
  362. tdc_spi_wr_code(0x70);
  363. tdc_spi_wr_code(0x04);
  364. if (cfg & TDC_CFG_DO_CKDIS){
  365. DMA_ReqClkOff();
  366. PeriClk_MutDisable(PeriClk_Spi1);
  367. }
  368. //rt_exit_critical();
  369. }
  370. void tdc_read_temp(uint32_t cfg)
  371. {
  372. //rt_enter_critical();
  373. if (cfg & TDC_CFG_DO_CKENA){
  374. PeriClk_MutEnable(PeriClk_Spi1);
  375. DMA_ReqClkOn();
  376. }
  377. TdcStatus = tdc_spi_rd_d16(0xd0); // status
  378. tdc_spi_wr_code(0x70);
  379. TdcPT[0] = tdc_spi_rd_d32(0xd1); // REF 5K +/- 5
  380. TdcPT[1] = tdc_spi_rd_d32(0xd2); // U7
  381. //TdcPT[2] = tdc_spi_rd_d32(0xc4); // U8
  382. //TdcPT[3] = tdc_spi_rd_d32(0xc5); // REF 1.5K
  383. // if (TdcPT[0]>0x1000000u && TdcPT[0]<0x2000000u){
  384. // TdcResist = 5000.0f*TdcPT[1]/TdcPT[0];
  385. // Ohm2Dgr2USSpd(TdcResist, WaterPrmt); // [0]:Temperature; [1]:ultrasonic speed @Temp
  386. // }
  387. if (TdcPT[0]>0xB00000u && TdcPT[0]<0xE00000u){
  388. TdcResist = 2500.0f*TdcPT[1]/TdcPT[0]; // ohmX10
  389. Ohm2Dgr2USSpd(TdcResist, WaterPrmt); // [0]:Temperature; [1]:ultrasonic speed @Temp
  390. }
  391. //LOG("----------T=%.6f,C=%.6f\n",WaterPrmt[0],WaterPrmt[1]);
  392. if (cfg & TDC_CFG_DO_CKDIS){
  393. DMA_ReqClkOff();
  394. PeriClk_MutDisable(PeriClk_Spi1);
  395. }
  396. //rt_exit_critical();
  397. }